This disclosure relates to testing of electronic elements, and more particularly to an apparatus and a method that measure propagation delay, setup time, and hold time of electronic elements under tests.
Accurate timing measurements of propagation delay, setup time, and hold time of electronic components are necessary to design modern electronic instruments and test systems. A way to describe the timing measurement of a signal is to characterize the signal as an edge, which is a transition between two voltage levels representing logic zero and logic one in a digital system, and specify the placement accuracy of that edge with respect to a specified position.
Automatic test systems designed to characterize or qualify integrated circuits (ICs) are frequently specified to have a signal edge placement accuracy measured in picosecond (ps), such asxc2x150 ps. The edge placement accuracy of such automatic test systems incorporates accumulated errors from a number of different components in the timing path of the automatic test systems. These components must be characterized and qualified with precision far better than the capability of the automatic test systems because the errors from each of these components accumulate in the path. In addition, if the errors are systematic errors, they may add directly depending on their nature. Furthermore, if the errors are due to random noise, they may add in quadrature (i.e., each error is squared and their sum square rooted). Thus, it is necessary to know very precisely the systematic and the random components of the timing errors introduced by all the components in the timing path of the automatic test systems in order to assure that the automatic test systems meet a specified edge placement accuracy.
There are many instruments designed to measure timing characteristics of electrical signals, including real-time oscilloscopes, sampling oscilloscopes, time interval meters, and spectrum analyzers. To measure their accuracy and stability, these instruments measure a signal passing through a precisely known delay path. The measurements of these instruments are compared to a time delay derived from the known length of the delay path. One such delay path is a coaxial signal line. In a coaxial signal line, the propagation delay of an electrical signal is known to be the speed of light in a vacuum multiplied by the inverse of the square root of the dielectric constant of the dielectric material separating the inner and outer conductors of the coaxial signal line. The dielectric material can be air if the coaxial signal line is rigid metal. The dielectric constant of air is well known at any given temperature and humidity. One such known coaxial signal line is formed from two variable-length rigid air-dielectric delay lines paired with a U-junction hereafter known as a xe2x80x9ctrombone.xe2x80x9d
A conventional high performance oscilloscope has an accuracy of xc2xd to 1 picoseconds. As the demand for more accurate automatic test equipment increases, the demand for more accurate instruments used to characterize and qualify the components of automatic test equipment also increases. Thus, what is needed is an instrument and method that can characterize and qualify electronic components (including integrated circuits and discrete components) of automatic test equipment with greater accuracy.
An apparatus is provided to compare the propagation delay of electronic elements such as transistors, integrated circuits, and interconnections for integrated circuits. The apparatus includes a strobe source having an output line coupled to a control terminal of a pattern source and an input terminal of a variable clock signal delay. The strobe source triggers the pattern source to output signal a predetermined sequence of logic signals which are xe2x80x9c0xe2x80x9ds and xe2x80x9c1xe2x80x9ds to an input terminal of the element or device under test (DUT). The DUT propagates the sequence of logic xe2x80x9c0xe2x80x9ds and xe2x80x9c1xe2x80x9ds to a first flip-flop (or other storage element). The first flip-flop propagates the signal received from the DUT to a second flip-flop (or other storage element) each time the first flip-flop is clocked by the variable clock signal delay. The second flip-flop propagates the signal received from the first flip-flop when it is clocked.
To compare the propagation delay of DUTs, the pattern source supplies the same sequence of logic xe2x80x9c0xe2x80x9ds and xe2x80x9c1xe2x80x9ds to each DUT. The variable clock signal delay is used to move the clock signal edge to the first flip-flop back and forth so that the first flip-flop receives the clock signal edge at substantially the same time as the data signal edge (i.e., the transition of the DUT output signal from one logic state to another). This timing alignment triggers the flip-flop into a known short-lived intermediate state called xe2x80x9cmetastabilityxe2x80x9d. The second flip-flop stores the output signal of the first flip-flop and ends the metastability of the first flip-flop.
When the first flip-flop receives the clock signal edge and the data signal edge at substantially the same time, the output signal of the first flip-flop is unpredictable (i.e., varies between logic xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d) at the normal propagation delay of the first flip-flop if the setup time or the hold time of the first flip-flop is violated. The range of time that the clock signal edge becomes so close to the data signal edge that the output signal is unpredictable at the normal propagation delay is called the metastable region. The range of time that the clock signal edge becomes so close to the data signal edge that the output signal is unpredictable after a period of time much larger than the normal propagation delay is called the ambiguity region. The ambiguity region can be made short if the output signal of the first flip-flop is given time beyond the normal propagation delay to settle. By moving the clock signal edge to the first flip-flop back and forth in time, the ambiguity region (with the data signal edge located therein) is determined from the output signal of the first flip-flop recorded by the second flip-flop. Thus, the data signal edge can be located with great precision if the second flip-flop propagates the output signal of the first flip-flop after a time extended beyond the normal propagation time of the first flip-flop (extended delay).
In one embodiment, the variable clock delay signal clocks the first flip-flop and the second flip-flop at the same time, which creates a one clock cycle delay to the propagation of the output signal of the first flip-flop by the second flip-flop. The one clock cycle of delay provides the extended delay needed to create a short ambiguity region to locate the data signal edge. After the delays of the variable clock delay that generate the ambiguity regions for the DUTs under the same input and the same extended delay are located, they can be compared to determine which DUT has the least propagation delay. Thus, the apparatus and associated method can characterize and qualify the propagation delays of different DUTs with great accuracy.
An apparatus is further provided to compare the setup time and the hold time .of DUTs. In one embodiment, the variable clock delay provides clock signals to the DUT. To compare the setup time and the hold time of the DUTs, the pattern source supplies the same sequence of logic signal xe2x80x9c0xe2x80x9ds and xe2x80x9c1xe2x80x9ds to each DUT. The variable clock delay is used to move the clock signal edge to each DUT back and forth so that the DUT receives the clock signal edge at substantially the same time as the data signal edge (i.e., the transition of the DUT input from one logic state to another). The first flip-flop is used to record the resulting output signal of the DUT.
When the DUT receives the clock signal edge at substantially the same time as the data signal edge, the resulting output signal of the DUT is unpredictable (i.e., varies between logic xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d) at a propagation delay of the DUT if the setup time or the hold time of the DUT is violated. The setup time of the DUT is not satisfied when the clock signal edge does not arrive sufficiently after the data signal edge. The hold time of the DUT is not satisfied when the clock signal edge does not arrive sufficiently prior to the data signal edge. Thus, the range of time that the clock signal edge becomes so close to the data signal edge that the output signal of the DUT is unpredictable (the ambiguity region) is the sum of the setup time and the hold time of the DUT at a propagation delay when the first flip-flop records the output signal of the DUT. By moving the clock signal edge back and forth, the ambiguity regions of each DUT at the same propagation delay is determined from the output signal of the DUT recorded by the first flip-flop.
In one embodiment, the variable clock delay clocks the DUT and the first flip-flop, which creates a one clock cycle delay to the propagation delay at which the first flip-flop records the output signal of the DUT. In other words, the setup time and the hold time of each DUT are determined at the propagation delay of one clock cycle. Once the delays of the variable clock delay that generate all the ambiguity regions of the DUTs at this propagation delay are determined, they can be compared to determine which DUT has the least setup time and hold time. Thus, the apparatus and associated method can characterize and qualify the setup time and the hold time of different DUTs with great accuracy.